1. Field of the Invention
Embodiments of the invention generally relate to a fabrication process for forming a metal containing layer on a substrate, and more particularly, for forming a metal containing layer into features defined in a material layers disposed on a substrate on semiconductor substrates.
2. Description of the Background Art
Reliably producing submicron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as the miniaturization of circuit technology is pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is very important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates.
As circuit densities increase for next generation devices, the widths of interconnects, such as vias, trenches, contacts, gate structures and other features, as well as the dielectric materials therebetween, decrease to 45 nm and 32 nm dimensions, whereas the thickness of the dielectric layers remain substantially constant, with the result of increasing the aspect ratios of the features. Many traditional deposition processes have difficulty filling submicron structures where the aspect ratio exceeds 4:1. For example, a metal containing layer deposited using a PVD process often suffer from poor step coverage, overhang, and voids formed within the via or trench when the via is less than 50 nm or having an aspect ratio greater than 4:1. Insufficient deposition on the bottom and sidewall of the vias or trenches can also result in deposition discontinuity, thereby leading to device shorting or poor interconnection formation. Therefore, there is a great amount of ongoing effort being directed at the formation of substantially void-free, seam-free and conformal submicron features having high aspect ratios and small dimensions.
Furthermore, as the feature sizes have become smaller and the aspect ratio of the features become higher, a deposition process is being required to deposit materials into features having good profile control and uniformity management. During deposition of a metal containing layer in a physical vapor deposition process, a gas mixture is typically supplied into the chamber to form a plasma to bombard materials from a target disposed in the chamber and deposit the dislodged materials sputtered from the target to deposit on a substrate surface. However, during depositing, the plasma as generated may not be uniformly distributed across the surface of the substrate, thereby resulting in deposition profile non-uniformity between the center and edge portions of the substrate. Non-uniform film deposition profile and thickness distribution may result in unwanted defects, and further adversely affect subsequent process steps, ultimately degrading or disabling the performance of the final integrated circuit structure.
Therefore, there is a need for an improved method of a metal containing layer into features on a substrate with high aspect ratios and small dimensions.